Published by Olivier Mathieu, Market Development Manager
Advanced Electronics Solutions

Silicon carbide (SiC) has outstanding properties which makes it a very useful material for power semiconductor devices in multiple applications, such as renewable energy systems and inverters for electric vehicles. However, the specific costs ($/cm²) of SiC devices are and will remain higher than silicon (Si) devices, though the cost ratio may change in the future. Therefore, it is necessary to not only consider possible savings regarding miniaturization and higher power density (kW/kg, kW/l) but to minimize expenditure for semiconductors as well. Multi chip packaging and substrate technologies play a major role in this equation.

Power density depends on switching frequency

Passive components such as capacitors, inductors and transformers represent a significant share of the power converter unit´s (PCU) total weight, volume and cost. Their size can be reduced when power semiconductor devices operate at higher switching frequency. This is possible with SiC MOSFETs because they do not generate tail current and a very low level of switching energy can be achieved. Consequently, switching losses mainly depend on switching time.

Fast switching speed has multiple limitations in the system as it may:

  • affect the driver circuit, due to parasitic capacitive coupling
  • generate overvoltage at turn-off because of parasitic inductance in the commutation path
  • lead to accidental turn-on because of parasitic drift of the gate voltage
  • reduce the lifetime of isolation materials in components, such as motors and transformers
  • negatively impact the electromagnetic compatibility of the system.

While higher switching speed is possible with SiC devices, the chip layout, the chip assembly, the interconnection technologies, and the ceramic substrate with its copper pattern all have a potential impact on parasitic inductance and coupling capacitances in the system. Therefore, the optimization of the chip packaging is important in order to take full advantage of the characteristics of these devices.

Power density depends on heat dissipation

The cooling circuit accounts for another large share of the system´s total weight, volume and cost. A size reduction can be achieved through an increase of the thermal resistance required to remove losses from the chip to the coolant.

A first approach is to increase the chip junction temperature. Silicon power devices are typically rated at 150°C up to 175°C and cannot tolerate a higher chip junction temperature because of the critical reverse leakage current. In contrast, wide band gap devices such as SiC MOSFETs can work at a higher chip junction temperature. The best device utilization is achieved at a chip junction temperature up to 250°C to avoid a thermal runaway as the current increases. Operation at a higher temperature is possible, but the current density should then be reduced. This lower chip utilization only makes sense in applications with an extremely high ambient temperature. In addition, operation at such a high chip junction temperature requires materials for die attach, interconnections and encapsulations with a suitable temperature resistance and a better match between their respective coefficient of thermal expansion (CTE) to reduce thermo-mechanical stress. Active metal brazed (AMB) silicon nitride (Si3N4) substrates have outstanding thermal and mechanical properties for use in such cases.

Reduction of the losses is another and even more promising approach. The high breakdown field of SiC material enables MOSFET structures with a thin drift layer to result in lower chip resistance. Consequently, conduction losses can be reduced. Even a slight reduction of the losses leads to a significant increase of thermal resistance. This is particularly true for systems with an existing high efficiency level and high-power rating. Ultimately, significant savings are possible for heat sinks and power consumption to drive fans and pumps for forced air cooling and liquid cooling, respectively.

Chip area must be optimized

Considering the cost distribution between different components in the system may vary depending on the application, the achieved savings in cooling and passive components may not be sufficient to compensate for the higher chip costs, due to the specific cost ($/cm²) of SiC devices. Therefore, the chip area must be optimized to achieve a decrease in specific system costs ($/kW). This can be either a system size reduction at the same power rating or a power rating increase at the same system size. Since the lower specific chip resistance and lower switching energy of SiC devices are given, operation at a high loss density and fast switching speed is the most effective approach to reduce the chip area. This requires a better heat dissipation. Again, active metal brazed (AMB) silicon nitride (Si3N4) substrates with high thermal conductivity and thick copper metallization is the technology of choice to support a broad adoption of SiC devices in multiple applications.

Do you have any question or require some information about our substrates? Please contact us if you need assistance.

Related Products:
curamik Ceramic Substrates

Olivier's Twist Blog, Automotive & EV/HEV

Published on Feb 25, 2021

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